Design of Efficient Parallel Self Timed Adders in TANNER EDA using GDI Technique

Abstract

This paper presents a parallel single-rail self-timed adder for adding multi-bit. In today's world there is a great need for low power design and high area efficient performance. Self-timed adders have the potential to run faster averaged for dynamic data. In existing PASTA system, high fanouts required but which could solve by connecting transistors in parallel manner. Even though which increases the design size. So that power consumption also increased. So here going to implement the new technique called GDI [Gate Diffusion Input]. This new implementation for reduction in power consumption, delay, transistor count more than PASTA. This design includes completion detection unit for the output generation. Simulation for the proposed design have been performed using Tanner Tool v14.11 and verify the practicality and working manner of the proposed approach over existing PASTA design.