Implementation of High Throughput and Reduced Complexity LDPC Decoder using Message Passing Algorithm

Abstract

In LDPC codes there is a tradeoff between decoder performance and decoder complexity. In order to overcome this problem a message passing algorithm for decoding LDPC codes is proposed in this paper. This algorithm is based on both hard and soft decision decoding techniques. The proposed algorithm for LDPC decoder has been implemented and tested on Xilinx vertex 5 FPGA, this implemented decoder can achieve a throughput of 23.2Gbps and also reduces the decoder complexity such as hardware resources.