Design and FPGA Implementation of Reliable SHA-3 Algorithm

Abstract

SHA-3 is one of the important cryptographic tools which is being used for system and information security. This cryptographic tool is used in assuring data integrity as changing one single bit in the input message can change about half of the output digest. The SHA-3 has been selected and will be used to provide security to applications requiring hashing, pseudo-random number generation and integrity checking. This algorithm has been chosen based on benchmarks such as security, performance and complexity. To provide reliable architectures for this algorithm an efficient concurrent error detection scheme is chosen for the proposed SHA-3 algorithm. The proposed error detection approach has less complexity and performance overheads while maintaining high error coverage. A low-complexity recomputing with RERO scheme reduces the hardware overhead of this error detection approach. This scheme is simulated on FPGA  and that has less complexity and performance overheads. The development of high-performance concurrent error detection scheme is expected to provide more reliable and robust hardware implementation for the newly-standardized SHA-3 algorithm.