Optimization And Analysis Of Tapered Buffer For Minimum Power Delay Using CMOS Technology

Abstract

 In this paper, an optimum stage ratio for a tapered CMOS inverter chain is derived to minimize the product of power dissipation This analysis is verified by simulation results using Microwind 3.5 simulator standard 120nm CMOS technology. The output parameters such as propagation delay, total chip area, threshold voltage, capacitance and power dissipation are calculated by using Microwind. The simulated results of the three multipliers are compared. From the analysis of these simulated results, it was found that the proposed Vedic multiplier circuit gives better performance