Fault Detection in Low Density Parity Check (LDPC) Codes

Abstract

Design of less decoding time of system is one of the largest areas of research in VLSI system design. The resent technology was proposed to accelerate the majority logic decoding of difference set low density parity check codes. This is useful as majority logic decoding can be implemented serially with simple hardware but requires large decoding time. For memory applications, this increases the memory access time. The method detects whether a word has errors in the first iterations of majority logic decoding, and when there are no errors the decoding ends without completing the rest of the iterations. Since most words in a memory will be error-free, the average decoding time is greatly reduced. In this brief the application of a similar technique to a class of Euclidean geometry low density parity check (EG-LDPC) codes that are one step majority logic decodable. The results obtained show that the method is also effective for EGLDPC codes. Extensive simulation results are given to accurately estimate the probability of error detection for different code sizes and numbers of errors