Design of High Performance Pipelined Data Encryption Standard (DES) Using Xilinx Virtex-6 FPGA Technology

Abstract

This paper describes the design of high performance Data encryption process is a predominant  symmetric-key algorithm for the encryption of electronic data. It was highly influential in the advancement of modern cryptography and it is easily be quite complicated and usually requires significant computation time and power despite significant simplifications. This discusses about the pipelined implementation and it is most commonly used symmetric encryption algorithm, Data Encryption Standard (DES). The platform used for this matter is, Xilinx new high performance silicon foundation, Virtex-6 Field Programmable Gate Array technology. The testing of the implemented design shows that it is possible to generate data in 16 clock cycles when non-pipelined approach is employed and then the pipelined approach is employed on the other hand, 17 clock signals are required for the initial phase only, and one clock signal is sufficient afterwards for each data generation cycle. In this, the Very High Speed Integrated Circuit Hardware Description  Language (VHDL) is used to program the design.