High Performance 64-bit Error Tolerent Adder Using Cadence Tool

Abstract

In the conventional adder circuit, the delay is mainly attributed to the carry propagation chain along the critical path, from the least significant bit (LSB) to the most significant bit (MSB). Also glitches in the carry propagation chain dissipate a significant proportion of dynamic power dissipation. Therefore, if the carry propagation can be eliminated or curtailed, a great improvement in speed performance and power consumption can be achieved, Delay and Power estimation for different number of bits is estimated.The power and area almost 50% reduced compared to conventional adder.