Comparative Analysis of Keeper Techniques for Domino Circuits

Abstract

Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. The main drawbacks of dynamic logic are lack of design automation and less tolerance to noise. In performance-critical applications, Domino logic is widely employed since it has a lower delay at the cost of reduced noise immunity, compared with static CMOS logic but still it is not preferred much for practical applications mainly due to delay variations and large power dissipation.In this work the comparative analysis of various domino keeper topology techniques for various important constraints such as power, area, speed and PDP has been done. These techniques are compared by detailed transistor simulation on benchmark circuits such as 2-bit OR gate using microwind 2 and DSCH 2 CMOS layout CAD tools.