Efficient Design of VLSI Architecture for Error Correction by using ML Decoder/Detector

Abstract

Error correction codes protect the memories from soft errors which cause data corruption. When additional protection is needed an advanced error correction codes are utilized. For correcting large number of soft errors, reduce decoding time and area consumption, majority logic decoder/detector codes are used. This paper presents an error detection method using majority logic decoding methodology for Euclidean Geometry Low Density Parity Check codes.  The codes are synthesized using Xilinx 8.1 and Modelsim 6.3g.The proposed improved majority logic detector/decoder to perform silent data error correction in simple way using additional error correction technique and also reducing the delay time by detecting the errors in parallel and pipelining manner. Hence the decoding process uses less number of cycles which reduces the delay and also reduces the power consumption.