Assertion Based Verification of I2C Master Bus Controller with RTC

Abstract

This paper implements serial data communication using I²C(Inter –Integrated Circuit) master bus controller using a field programmable gate array(FPGA).The I²C master bus controller is interfaced with MAXIM DS1307,which acts as a slave. This module is designed in Verilog HDL and simulated in Questa sim 6.4 c. The design is synthesized using Xilinx ISE Design suite 14.2. I²C master initiates data transmission and in order slave responds to it. It can be used to interface low speed peripherals like mother board, embedded system, mobile phone, set top boxes ,DVD,PDA's or other electronics devices.