Design and Verification of DDR SDRAM Controller for Satelite Data Acquisition System

Abstract

DDR SDRAM, with features of large capacity and high speed, has a good prospect in the acquisition of satellite navigation system which requires large amounts of data accumulation. A Dedicated Memory Controller is of prime importance in applications that do not contain microprocessors (high-end applications). The Memory Controller provides command signals for memory refresh, read and write operation and initialization of SDRAM. Our work will focus on ASIC Design methodology of Double Data Rate (DDR) SDRAM Controller that is located between the DDR SDRAM and Bus Master. The Controller simplifies the SDRAM command interface to standard system read/write interface and also optimizes the access time of read/write cycle. Double Data Rate (DDR) SDRAM Controller is implemented using Cadence RTL Compiler.