Design and Implementation of High Speed Binary Comparator Using QCA Technology

Abstract

As the size of CMOS transistors keep shrinking, it will eventually hit its limitation. Hence an alternative device has to be discovered to continually improve the development of electronics devices. Quantum dot cellular automata (QCA) are an attractive emerging technology suitable for the development of ultra dense low power high performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adder, multipliers, and comparators. This work proposes a new design approach oriented to implementation of binary comparators in QCA. The proposed QCA based comparator has been designed using verilog and simulated using Xilinx 9.1. The comparator proposed here exhibit significantly higher speed and reduced over all area with respect to exhibiting comparators, this is due to elimination of long carry chain of checking bits from MSB to LSB in proposed comparator