Adaptive FIR Filter with High Throughput and Low Power Consumption

Abstract

In this manuscript, an adaptive fir filter for power efficient, area efficient and high throughput design will be delegating using distributed arithmetic (DA). DA is a bit serial computational action and uses set of smaller dynamic parallel look up tables (LUTs), equivalent concurrent realization of filtering weight update proposal for improving the throughput rate. To reduced area complexity, sampling period and critical path, the conditional carry save accumulation of shift accumulator using 10 Transistors circuitry will used in placed of conventional adder based shift accumulation. The Least mean square (LMS) algorithm is introduced to update weight and decline the mean square root error between desired and expected output. For the diminution in power consumption of proposed design, the two separate clocks are introduced; one bit clock for carry save accumulation and it is fastest clock whereas slower for all other computations. The proposed design will include no. of multiplexer, very less no. of LUTs and full adder using half adders.