A Novel Approach of Delay-Insensitive Null Convention Logic Microprocessor Design

Abstract

Null Convention Logic (NCL) has the potential advantage of Delay insensitivity and Low Power when compared to other asynchronous VLSI design methodologies [1]. This paper has arisen focusing on exploiting the advantages of clock less NCL asynchronous design. The paper proposes the design of 8 bit Asynchronous Microprocessor using NCL Method: The Processor consists of various sub modules (like).   We have proposed Half adder sub module using NCL. Results: We implemented a half adder where the data was sequenced synchronously and asynchronously, which yielded an average delay of 22.5ns, 7.5ns respectively. The same design methodology can be extended to the other sub modules of processor which can operate at a higher speed when compared with a synchronous processor.     Performance analysis: We also made a comparative analysis of various asynchronous designs and NCL based circuit designs. Conclusion: These results provide a firm platform for designing Asynchronous Null convention logic based Microprocessor.