Efficient VLSI Architecture for CMOS Image Sensor with Reconfigurable Array Processing

Abstract

Digital CMOS Image Sensor (CIS) are an attractive emerging technology. It is possible to use cameras and other imaging system. Several vlsi architecture have been proposed like active pixel sensor and passive pixel sensor and CCD. They have some limitation in architecture and dynamic range and SNR and resolution level. This paper presents a CMOS image sensor (CIS) VLSI architecture based on reconfigurable PWM and array processing. Resolution in the image sensor will be depends upon the no of pixel in the array format. Array format can be used 512x512 pixels, 256x256 pixels, 128x128 and also 64x64 pixels. The presented VLSI architecture for CMOS Image sensor can perform all above mentioned array format. This architecture achieves higher dynamic range and good SNR and also various resolution based image can be obtained. High readout capability obtained.