KAUR, R.; SINGH, R.; NAG, V. R. Optimization And Analysis Of Tapered Buffer For Minimum Power Delay Using CMOS Technology. The International Journal of Science & Technoledge, [S. l.], v. 1, n. 11, 2013. Disponível em: http://internationaljournalcorner.com/index.php/theijst/article/view/128084. Acesso em: 7 jul. 2024.