S., T. M. P.; CHOWDHARY, S. V.; UDARA, S. High Performance 64-bit Error Tolerent Adder Using Cadence Tool. The International Journal of Science & Technoledge, [S. l.], v. 2, n. 8, 2014. Disponível em: http://internationaljournalcorner.com/index.php/theijst/article/view/128176. Acesso em: 7 jul. 2024.