PARAMESWARI, S. N. L.; BABU, G. R. M. Efficient Design of VLSI Architecture for Error Correction by using ML Decoder/Detector. The International Journal of Science & Technoledge, [S. l.], v. 2, n. 3, 2014. Disponível em: http://internationaljournalcorner.com/index.php/theijst/article/view/138591. Acesso em: 17 jul. 2024.