S., Tejo Murthy P., Sanjay V. Chowdhary, and Srinivasarao Udara. 2014. “High Performance 64-Bit Error Tolerent Adder Using Cadence Tool”. The International Journal of Science & Technoledge 2 (8). http://internationaljournalcorner.com/index.php/theijst/article/view/128176.