S., T. M. P., Chowdhary, S. V. and Udara, S. (2014) “High Performance 64-bit Error Tolerent Adder Using Cadence Tool”, The International Journal of Science & Technoledge, 2(8). Available at: http://internationaljournalcorner.com/index.php/theijst/article/view/128176 (Accessed: 7 July 2024).