Kaur, Rajneet, Randhir Singh, and Vibha Raj Nag. “Optimization And Analysis Of Tapered Buffer For Minimum Power Delay Using CMOS Technology”. The International Journal of Science & Technoledge 1, no. 11 (November 30, 2013). Accessed July 7, 2024. http://internationaljournalcorner.com/index.php/theijst/article/view/128084.