Area Efficient Modular Multiplier for Cryptography Applications

Abstract

The Modular multiplier is the basic building block of cryptograpic processors. This is used widely for unique applications like network security and high speed performance in multi-core processors. It mainly requires efficient and reliable hardware implementations. The classical methods have limitations in size of intermediate quotient. To overcome this, Column compression multiplier algorithm is used with the parallel implementation of Barett reduction and Montgomery reduction and Karatsuba algorithm. These are basic mathematical algorithms. Applying digit serial implementation among these three multipliers, low area is obtained compared to the existing multiplier algorithms. The experimental results shown here, which is obtained from XILINX ISE, SPARTAN 2E Family, mainly concentrates on area by considering the number of gates used for the digit serial implementation.