Design of Low Power Reversible Multiplier

Abstract

Reversible logic has received great attention in recent years due to their ability to reduce the power dissipation which is the main requirement in low power VLSI design. The classical set of gates such as AND, OR and EXOR are not reversible. This paper proposes a 4x4 bit reversible multiplier circuit using Peres gate which can multiply two 4-bit numbers. It is faster and has low hardware complexity compared to the existing designs. In addition, this reversible multiplier is better than the existing counterparts in terms of delay and power because the Peres gate reduces the garbage output. It is based on two concepts, The partial products can be generated in parallel using Peres gates and thereafter the addition is done by using reversible parallel adder designed from Peres gates. Thus, this paper provides the initial threshold to building of more complex system which can execute more complicated operations using reversible logic.