A Novel Low Power Pulsed Latch with Increased Reliability

Abstract

The maturation in fabrication technologies of semiconductor integrated circuits results in rapidly shrinking technology node and aggressive scaling of voltage causes an increase in the probability of soft errors in advanced CMOS digital logic circuits. Many attempts to mitigate the soft errors ensue in significant cost penalties in terms of area, power and performance. The proposed method intents a pulsed latch with increased immunity, reliability and reduced power consumption for this purpose, a new transition detector is designed in order to detect single event transition. It shows a remarkable melioration in terms of power, area and performance when compared to conventional transition detector post layout simulation using CMOS 45nm. This detector is further engrafted into the latch to be used as register. The reliability and effectual functioning of proposed pulsed latch is compared with conventional register. The proposed system is designed using MICROWIND 3.1 to get efficacious output.