Co-verification of Registers Using UVM RAL

Abstract

The technological development has led to rapid increase in the complexity of system design, whereas the system design gap is also increasing because of Moores law. Hardware dependent software (HdS) is addressing system design gap challenge by providing close interface between software and hardware. The co-verification of hardware and software thus becomes a critical task which is needed to be performed at system level for functional verification. Hardware registers are responsible for initial configuration of Design Under Test and hence their verification is vital for creation of error free test-bench environment. In System Verilog UVM Register Abstraction Layer (RAL) provides flexibility and reusability of register models but some run time overheads are incurred in System Verilog which limits the effective exploitation of UVM RAL. Multi core verification language Vlang has been used in this paper to efficiently employ UVM RAL without any overheads of speed and memory. AMBA AHB –Lite Master interface with I2C Core is used for co-verification of I2C register.