Design and Implementation of Optimized Floating Point Matrix Multiplier Based on FPGA

Abstract

In computing, floating point describes a method of representing an approximation in real numbers that can support a wide range of values. A binary multiplier is an integral part of the ALU subsystem found in many processors. Integer multiplication can be inefficient and costly, in time and hardware, depending upon the representation of signed numbers. Booth algorithms suggest technique for multiplying signed numbers that works well for both positive and negative multipliers. This work modifies Weng and Duh's design with modified Booth multiplier in multiplication to reduce the number of partial products. As a result, the improved floating point matrix multiplier having better performance with shorter delay has been designed compared to Weng and Duh's design.