Data Concentration and Archival to SD Card in Verilog Language

Abstract

Smart Grid (SG) is the next generation's power grid system. Delivering control, monitoring and management data to grid elements often requires the efficient archival of acquired information. The main objective of this research is to design an experimental platform for efficient, on-chip, real-time data concentrator for accessing data from a Secure Digital flash memory card using the SD bus protocol. All the hardware design is done using Verilog hardware descriptive language and implemented in Field Programmable Gate Array (FPGA). The design has four independent modules for the required different operations on the SD memory card. These four modules are for single block write, multiple block write, single block read, and multiple block read operations. A temporary data is either stored internally in an array of registers or externally in the Synchronous RAM for the analysis purposes. The design is implemented on the Altera's Cyclone II EP2C35F672C6 FPGA chip using 1GB SanDisk SD card and has shown a maximum data concentration rate of 25 Mbps.