Design and Verification of ADPLL for SERDES

Abstract

This project aims towards design of ADPLL (all digital phase lock loop) using Verilog and its verification using Verilog verification methodology. ADPLL is a building block for most high speed digital functional blocks such as SEDRES (Serialization and de-serialization) for clock synchronization. Quistasim/multisim Simulator is used for simulating Verilog Code. This project gives details of the basic blocks of an ADPLL. In this project it is been planned to implementation of ADPLL. Its simulation results are verified for all the corners of inputs. The ADPLL is planned for 200 MHz central frequency. The operational frequency range of ADPLL is 189 KHz to 215 MHz, which is lock range of the design.